release/21.x: Mips: Improve MipsAsmParser::expandDivRem (#172967) #173321
+1,559
−1,233
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Fixes: llvm#172965 In fact MipsAsmParser::expandDivRem is in a so bad status: 1. Div may not execute at all in most case ``` .set reorder bnez $3, $tmp0 div $zero, $2, $3 break 7 $tmp0: ``` `.set reorder` may insert a nop after bnez, which will skip `div` if $3 is not zero. 2. `break 6` is wrong here. (cherry picked from commit c907d7d)
Member
Author
|
@llvm/pr-subscribers-backend-mips Author: None (llvmbot) ChangesBackport c907d7d Requested by: @wzssyqa Patch is 208.60 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/173321.diff 12 Files Affected:
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 602b89a117595..d541e95045053 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -68,6 +68,7 @@ class MCInstrInfo;
} // end namespace llvm
extern cl::opt<bool> EmitJalrReloc;
+extern cl::opt<bool> NoZeroDivCheck;
namespace {
@@ -4230,7 +4231,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (!ATReg)
return true;
- if (ImmValue == 0) {
+ if (!NoZeroDivCheck && ImmValue == 0) {
if (UseTraps)
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
else
@@ -4262,7 +4263,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
// break, insert the trap/break and exit. This gives a different result to
// GAS. GAS has an inconsistency/missed optimization in that not all cases
// are handled equivalently. As the observed behaviour is the same, we're ok.
- if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
+ if (!NoZeroDivCheck && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
if (UseTraps) {
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
return false;
@@ -4283,62 +4284,25 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
MCSymbol *BrTarget;
MCOperand LabelOp;
- if (UseTraps) {
- TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
- } else {
- // Branch to the li instruction.
- BrTarget = Context.createTempSymbol();
- LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
- TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
- }
-
TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
+ if (!NoZeroDivCheck) {
+ if (UseTraps) {
+ TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
+ } else {
+ // Branch to the li instruction.
+ BrTarget = Context.createTempSymbol();
+ LabelOp =
+ MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
+ TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
+ }
- if (!UseTraps)
- TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
+ if (!UseTraps)
+ TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
- if (!Signed) {
if (!UseTraps)
TOut.getStreamer().emitLabel(BrTarget);
-
- TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
- return false;
- }
-
- MCRegister ATReg = getATReg(IDLoc);
- if (!ATReg)
- return true;
-
- if (!UseTraps)
- TOut.getStreamer().emitLabel(BrTarget);
-
- TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
-
- // Temporary label for the second branch target.
- MCSymbol *BrTargetEnd = Context.createTempSymbol();
- MCOperand LabelOpEnd =
- MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));
-
- // Branch to the mflo instruction.
- TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
-
- if (IsMips64) {
- TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
- TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
- } else {
- TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
- }
-
- if (UseTraps)
- TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
- else {
- // Branch to the mflo instruction.
- TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
- TOut.emitNop(IDLoc, STI);
- TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
}
- TOut.getStreamer().emitLabel(BrTargetEnd);
TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
return false;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 1be29cf3c94b9..a44384d04d431 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -20,6 +20,10 @@ cl::opt<bool>
EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
cl::init(true));
+cl::opt<bool>
+ NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
+ cl::desc("MIPS: Don't trap on integer division by zero."),
+ cl::init(false));
namespace {
static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index ec6b382151660..70a76f5730e3b 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -81,12 +81,8 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
-static cl::opt<bool>
-NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
- cl::desc("MIPS: Don't trap on integer division by zero."),
- cl::init(false));
-
extern cl::opt<bool> EmitJalrReloc;
+extern cl::opt<bool> NoZeroDivCheck;
static const MCPhysReg Mips64DPRegs[8] = {
Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
diff --git a/llvm/test/CodeGen/Mips/divrem-inline-asm.ll b/llvm/test/CodeGen/Mips/divrem-inline-asm.ll
new file mode 100644
index 0000000000000..9dea24582138a
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/divrem-inline-asm.ll
@@ -0,0 +1,370 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
+
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
+
+; FileCheck Prefixes:
+; ALL - All targets
+; ACC64 - Same as ACC32 but only for 64-bit targets
+; GPR64 - Same as GPR32 but only for 64-bit targets
+; ACC64-TRAP - Same as TRAP and ACC64 combined
+; GPR64-TRAP - Same as TRAP and GPR64 combined
+; NOCHECK - Division by zero will not be detected
+
+
+define i32 @inline_asm_div() {
+; ACC64-TRAP-LABEL: inline_asm_div:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: addiu $2, $zero, 2
+; ACC64-TRAP-NEXT: addiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: div $zero, $2, $3
+; ACC64-TRAP-NEXT: bnez $3, .Ltmp0
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp0:
+; ACC64-TRAP-NEXT: mflo $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_div:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: addiu $2, $zero, 2
+; NOCHECK-NEXT: addiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: div $zero, $2, $3
+; NOCHECK-NEXT: mflo $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i32 asm sideeffect "div $0, $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i32 2, i32 1)
+ ret i32 %0
+}
+
+define i32 @inline_asm_rem() {
+; ACC64-TRAP-LABEL: inline_asm_rem:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: addiu $2, $zero, 2
+; ACC64-TRAP-NEXT: addiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: div $zero, $2, $3
+; ACC64-TRAP-NEXT: bnez $3, .Ltmp1
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp1:
+; ACC64-TRAP-NEXT: mfhi $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_rem:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: addiu $2, $zero, 2
+; NOCHECK-NEXT: addiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: div $zero, $2, $3
+; NOCHECK-NEXT: mfhi $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i32 asm sideeffect "rem $0, $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i32 2, i32 1)
+ ret i32 %0
+}
+
+define i64 @inline_asm_ddiv() {
+; ACC64-TRAP-LABEL: inline_asm_ddiv:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: daddiu $2, $zero, 2
+; ACC64-TRAP-NEXT: daddiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: ddiv $zero, $2, $3
+; ACC64-TRAP-NEXT: bne $3, $zero, .Ltmp2
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp2:
+; ACC64-TRAP-NEXT: mflo $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_ddiv:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: daddiu $2, $zero, 2
+; NOCHECK-NEXT: daddiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: ddiv $zero, $2, $3
+; NOCHECK-NEXT: mflo $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i64 asm sideeffect "ddiv $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i64 2, i64 1)
+ ret i64 %0
+}
+
+define i64 @inline_asm_drem() {
+; ACC64-TRAP-LABEL: inline_asm_drem:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: daddiu $2, $zero, 2
+; ACC64-TRAP-NEXT: daddiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: ddiv $zero, $2, $3
+; ACC64-TRAP-NEXT: bne $3, $zero, .Ltmp3
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp3:
+; ACC64-TRAP-NEXT: mfhi $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_drem:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: daddiu $2, $zero, 2
+; NOCHECK-NEXT: daddiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: ddiv $zero, $2, $3
+; NOCHECK-NEXT: mfhi $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i64 asm sideeffect "drem $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i64 2, i64 1)
+ ret i64 %0
+}
+
+define i32 @inline_asm_divu() {
+; ACC64-TRAP-LABEL: inline_asm_divu:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: addiu $2, $zero, 2
+; ACC64-TRAP-NEXT: addiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: divu $zero, $2, $3
+; ACC64-TRAP-NEXT: bnez $3, .Ltmp4
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp4:
+; ACC64-TRAP-NEXT: mflo $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_divu:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: addiu $2, $zero, 2
+; NOCHECK-NEXT: addiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: divu $zero, $2, $3
+; NOCHECK-NEXT: mflo $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i32 asm sideeffect "divu $0, $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i32 2, i32 1)
+ ret i32 %0
+}
+
+define i32 @inline_asm_remu() {
+; ACC64-TRAP-LABEL: inline_asm_remu:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: addiu $2, $zero, 2
+; ACC64-TRAP-NEXT: addiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: divu $zero, $2, $3
+; ACC64-TRAP-NEXT: bnez $3, .Ltmp5
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp5:
+; ACC64-TRAP-NEXT: mfhi $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_remu:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: addiu $2, $zero, 2
+; NOCHECK-NEXT: addiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: divu $zero, $2, $3
+; NOCHECK-NEXT: mfhi $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i32 asm sideeffect "remu $0, $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i32 2, i32 1)
+ ret i32 %0
+}
+
+define i64 @inline_asm_ddivu() {
+; ACC64-TRAP-LABEL: inline_asm_ddivu:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: daddiu $2, $zero, 2
+; ACC64-TRAP-NEXT: daddiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: ddivu $zero, $2, $3
+; ACC64-TRAP-NEXT: bne $3, $zero, .Ltmp6
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp6:
+; ACC64-TRAP-NEXT: mflo $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_ddivu:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: daddiu $2, $zero, 2
+; NOCHECK-NEXT: daddiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: ddivu $zero, $2, $3
+; NOCHECK-NEXT: mflo $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i64 asm sideeffect "ddivu $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i64 2, i64 1)
+ ret i64 %0
+}
+
+define i64 @inline_asm_dremu() {
+; ACC64-TRAP-LABEL: inline_asm_dremu:
+; ACC64-TRAP: # %bb.0: # %entry
+; ACC64-TRAP-NEXT: daddiu $2, $zero, 2
+; ACC64-TRAP-NEXT: daddiu $3, $zero, 1
+; ACC64-TRAP-NEXT: #APP
+; ACC64-TRAP-NEXT: .set push
+; ACC64-TRAP-NEXT: .set at
+; ACC64-TRAP-NEXT: .set macro
+; ACC64-TRAP-NEXT: .set reorder
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: ddivu $zero, $2, $3
+; ACC64-TRAP-NEXT: bne $3, $zero, .Ltmp7
+; ACC64-TRAP-NEXT: break 7
+; ACC64-TRAP-NEXT: .Ltmp7:
+; ACC64-TRAP-NEXT: mfhi $2
+; ACC64-TRAP-EMPTY:
+; ACC64-TRAP-NEXT: .set pop
+; ACC64-TRAP-NEXT: #NO_APP
+; ACC64-TRAP-NEXT: jr $ra
+; ACC64-TRAP-NEXT: nop
+;
+; NOCHECK-LABEL: inline_asm_dremu:
+; NOCHECK: # %bb.0: # %entry
+; NOCHECK-NEXT: daddiu $2, $zero, 2
+; NOCHECK-NEXT: daddiu $3, $zero, 1
+; NOCHECK-NEXT: #APP
+; NOCHECK-NEXT: .set push
+; NOCHECK-NEXT: .set at
+; NOCHECK-NEXT: .set macro
+; NOCHECK-NEXT: .set reorder
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: ddivu $zero, $2, $3
+; NOCHECK-NEXT: mfhi $2
+; NOCHECK-EMPTY:
+; NOCHECK-NEXT: .set pop
+; NOCHECK-NEXT: #NO_APP
+; NOCHECK-NEXT: jr $ra
+; NOCHECK-NEXT: nop
+entry:
+ %0 = tail call i64 asm sideeffect "dremu $1, $2", "=r,r,r,~{hi},~{lo},~{$1}"(i64 2, i64 1)
+ ret i64 %0
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; ACC64: {{.*}}
+; ALL: {{.*}}
diff --git a/llvm/test/MC/Mips/macro-ddiv.s b/llvm/test/MC/Mips/macro-ddiv.s
index 82342a29686f0..c1c2468c9ac86 100644
--- a/llvm/test/MC/Mips/macro-ddiv.s
+++ b/llvm/test/MC/Mips/macro-ddiv.s
@@ -4,351 +4,298 @@
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
ddiv $25,$11
-# CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
-# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
-# CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
-# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
-# CHECK-NOTRAP: .Ltmp0
-# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
-# CHECK-NOTRAP: bne $11, $1, .Ltmp1 # encoding: [0x15,0x61,A,A]
-# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
-# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
-# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
-# CHECK-NOTRAP: bne $25, $1, .Ltmp1 # encoding: [0x17,0x21,A,A]
-# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
-# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
-# CHECK-NOTRAP: .Ltmp1
-# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
-
-# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
-# CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
-# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
-# CHECK-TRAP: bne $11, $1, .Ltmp0 # encoding: [0x15,0x61,A,A]
-# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
-# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
-# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
-# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
-# CHECK-TRAP: .Ltmp0:
-# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
+// CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
+// CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
+// CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
+// CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
+// CHECK-NOTRAP: .Ltmp0:
+// CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
+// CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
+// CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
+// CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
+
ddiv $24,$12
-# CHECK-NOTRAP: bne $12, $zero, .Ltmp2 # encoding: [0x15,0x80,A,A]
-# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
-# CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
-# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
-# CHECK-NOTRAP: .Ltmp2:
-# CHECK-N...
[truncated]
|
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Backport c907d7d
Requested by: @wzssyqa